SMASH Evolution over time     SMASH 5.11 Efficient Mixing of Blocks - June 2008 Performing true mixed-signal simulations, as needed by a growing proportion of SoCs, requires bringing together analog blocks, from a schematic based analog design flow on a purely analog simulator, and logic blocks, from a batch based HDL design flow on a purely logic simulator. As the mixed-signal simulator for SoCs, SMASH provides both the analog and logic capabilities to directly simulate with the original models, while adding the circuit and testbench setup capabilities needed to perform complete mixed-signal simulations. SMASH 5.11 delivers enhanced ease of simulation setup and analysis while simplifying reuse of analog blocks with HDL in mixed-signal simulations! Presentation sheet     ................................................................................................................................ SMASH 5.10 Analog Power Analysis & Debug - December 2007 To overcome SoC integration challenges for increased performance, higher density, and reduced power consumption, designers must employ hierarchical budget allocation and analysis techniques. Constraints must be assigned harmoniously to the components of the System for power, noise… In order to maintain its lead in diagnostic know-how, not only does SMASH provide hierarchical extraction and tracing of power and noise, but it facilitates Virtual Test by enabling floating net detection during simulation to spot high impedance nets otherwise noticed too late during real test. Presentation sheet   ................................................................................................................................ SMASH 5.9 Mixed signal Debug - June 2007 SoC developers spend 70 % of their time debugging their design and analyzing unexpected or out-of-specification results. Improving productivity is therefore essential for the time-to-market requirements of today’s SoC. To that end, SMASH 5.9 introduces debug techniques, which have been successfully used in application software development, and adapts them to the world of transient simulation on HDL-AMS descriptions for efficient back-tracing on break points, in association with graphical access to the hierarchy of the design. Analog designers will appraise further improvements in their domain, such as new and updated SPICE models, phase noise extraction… Presentation sheet   ................................................................................................................................ SMASH 5.8 Mixed signal Diagnosis - December 2006 SMASH 5.8 extends its capabilities for mixed signal code-coverage and sensitivity-analysis up to detecting flaws in Virtual Testbenches and to identifying circuit weaknesses for the DfM conscious designer. Improvement on the block-busting GUI features facilitate further the adjustments of speed versus accuracy, as well as tracing, now augmented for a hierarchical view applicable to mixed signal design. Presentation sheet   ................................................................................................................................ SMASH 5.7 Empowered Mixity - June 2006 SMASH 5.7 is loaded with innovative features which contribute to increasing the productivity of logic, analog and mixed signal designers. With good estimates of power consumption in logic circuits, designers can make an educated selection of low-power architectures and of logic blocks. Now, for the first time, a simulator popularizes the setup of parameters to obtain the appropriate speed/accuracy tradeoff for a given Virtual Test. Presentation sheet   ................................................................................................................................ SMASH 5.6 Verilog-AMS joining VHDL and SPICE - December 2005 As the market is moving to nanometer technologies, the critical issue of transient noise takes a new urgency due to the sensitivity of analog and mixed-signal circuits, and even pure logic circuits. This is of course the case for PLL or oscillator designs, but also for evaluating the impact of noise injected by logic onto analog circuits. SMASH 5.6 eases the practice of transient noise analysis, while leveraging model specific noise equations such as TSMC specific equations. Presentation sheet   ................................................................................................................................ SMASH 5.5 enriched with Verilog-A - June 2005 Verilog-AMS benefits designers by allowing them to describe and simulate analog and mixed signal designs using a top-down design methodology as well as the traditional bottom up approach. Moreover, Verilog-AMS provides powerful structural and behavioral modeling capabilities for systems in which the effects of, and interactions among, different disciplines like electrical, mechanical and thermal are important. SMASH 5.5 extends its natively mixed-language and mixed-signal single kernel to Verilog-A with seamless hierarchical mixing with SPICE. Presentation sheet   ................................................................................................................................ SMASH 5.4 for Design Reliability & Yield - December 2004 Confronted with ever larger circuits and ever smaller fabrication technologies, Design Reliability & Yield investigation, beyond mere assessment, is required in order to obtain acceptable fabrication yield. Obviously, for effective RoI, the ever increasing fabrication cost mandates single-spin tape-outs! SMASH focuses on enhancing Design Reliability Analysis as well as simplifying and empowering Virtual Characterization. Presentation sheet   ................................................................................................................................ SMASH 5.3 - June 2004 Due to the ever-lasting need for performance improvements, mixed signal designers face the on-going pressure of time-to-market and of cost reduction. The main improvements provided in SMASH 5.3. are focused on increasing designers’ productivity for optimizing the reliability and yieldof complex circuits. Presentation sheet   ................................................................................................................................ SMASH 5.2 - December 2003 Beyond the stage when new functionality was on high demand, the last couple of years has led SMASH to focus rather on Designer's productivity gains. Concern for return on assets has generated new demands, ranging from Virtual test and Diagnostics, via the specialization for Front-End and Back-End, to yield assessment. Thanks to a new patent (pending), a proprietary "FAST" mode speeding up analog simulation, for high-risk circuits where small time steps are needed with intensive iterations, 3 times with an accuracy loss of 1%, and up to 7 times faster when accuracy can be relaxed! No other contender can do this... SMASH interfaces directly with Simulink/MATLAB. Users can leverage our unique mixed-signal multi language simulation technology in a system simulation: the ultimate top-down and bottom-up calibration and verification process that brings your HDL blocks back into your system specification!   ................................................................................................................................ SMASH 5.1 - June 2003 Upon mixity improvements SMASH 5.1 introduces drastic speed improvements to increase designers' productivity: Memory optimizations for large SPICE circuits Impressive speed improvements for second and third order VHDL-AMS models, particularly important for complex MEMS designs Mixity improvements such as ordered port mapping of VHDL instances in Verilog modules Support of cosimulation with SystemC models (a specific tutorial is available) Graphic interface improvements (Windows XP look, configurable tool bar, ...)

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