# 6 - SUCCESS with communicating Processors and Mixed Signal Peripherals |
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SUCCESS™ is the multi-domain cosimulation solution from DOLPHIN, coupling SMASH,
time domain simulator with any application program in C run on an Instruction
Set Simulator (ISS).
It meets different challenges like decreasing simulation time, increasing
debug thoroughness and allowing system simulation (involving microprocessor
with application programs and peripherals).
| Case of a dumb peripheral
device |
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Five layers are simulatable with a pair
of models:
- Application program (on the µP) for instance
for file encryption
- Operating system (optional, on the µP) such
as MS-Windows, Linux, or an embedded Real-Time Operating System (RTOS)
- Driver (µP software) for transmission sequence
Macros
- Device controller (electronics) with µP interface
(state register)
- Peripheral device (electromechanics) such as: in
the case of phone line with fuse short/open and busy state signals
| Case of an intelligent
peripheral |
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E.g. the 8051 µC as adhoc standard controller
for keyboards
• A higher layer is involved: the ultimate
user program in the Central Processing Unit (CPU)
The 8051 must be a peripheral on the central bus and must be a good
driver serving the CPU |
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SUCCESS accelerate your Time-to-Market
Case of an HDLC (High Data Link Controller)
| Preparing Industrial Test programs |
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Ultimately, there is a industrial test
program in C for sequencing, upon a
real HDLC out of fab, a series of test patterns stored as data in
some
spreadsheet format. |
Using SUCCESS for preparing Industrial Test
« programs » enables you to use the same test
sequences. You can debug your program virtually, in order to accelerate
your Time-to-Market.
The test sequences can be represented as:
- a spreadsheet for time series of a circuit inputs
and outputs with binary figures for logic signals and real numbers
for analog signals.
- a C program controlling the transfers of I/O signals over a system
bus.
- a set of VHDL/Verilog models of generators for sources and probes
for such I/O signals.
Synoptic view of the Virtual Component HDLC
Representation of an HDLC embedded within a SoC
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The data is sent/received by the CPU to/from the
HDLC
Through the System Bus |
HDLC as communicating component between two SoC’s
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To test the validity of the transmission w.r.t.
the protocol, the HDLC interface must be observed by some “TestBench”. |
Two HDLC’s talking to each other, one which sends
the data, another which receives the information:
a TestBench performs the comparison of data.
One of the HDLC is the Device
Under Test” (DUT), the other is part of the TestBench.
TestBench objectives for facilitating the integration
of an HDLC into a SoC
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The Virtual
TestBench serves only to check-up the ViC wherever it is, and
in particular that it is not altered along the integration process. |
The embedded HDLC is represented on the left on the SoC
Under Test.
The objectives of the Virtual Testbench are to send commands to both
HDLC’s and to control the data transmitted by the two HDLC’s
to each other.
Virtual TestBench for the HDLC
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Along the way from Virtual Test in design
to Industrial Test in a fab, a C
program enables an intermediate stage of Prototype Test in a Lab,
for
functional validation with a development kit on some PC. This development
tool must contain a real HDLC product as the physical "distant
HDLC" to communicate with. SUCCESS enables the stage of Virtual
Testing to
prepare both the functional validation sequences and the industrial
test
patterns. |
The C program sends data to the Device Under Test (HDLC
on the left). The HDLC on the right serves both as an interlocutor (same
protocol) and as the reference to conclude whether the behavior of the
device is correct or not.
The Test Bench is then a “meta-driver”, as it must test
all possible configurations.
Evolving to SUCCESS for dealing with HDLC control
within SoC
Going onto SUCCESS, the test sequencing is run in C in
the application program of the 8051 µP.
The VHDL Test Controller checks the communication between the two HDLC
as well as the behavior of the HDLC of reference.
(*) Transcoded from VHDL to C
Toward SUCCESS for Virtual Integration of HDLC
into your SoC
| Dealing with both
ends from our standard controller: Flip8051 |
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Test sequences and decisions are executed in C in
the ISS of the micro-controller. RAM and HDLC are modeled in SMASH. |
| Up to Driver Development for
HDLC |
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| SUCCESS allows to develop and test your SoC peripheral
driver software. |
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SUCCESS with Mixed Signal Peripherals
Design reliability thanks to hardware/software cosimulation
< SMASH Differentiators
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