Power Consumption of logic parts of a SoC is one face of the coin, the other face of which is Noise Resilience of analog parts. Reducing the peaks of a dynamic mixed-signal power consumption simulation grants the consistent benefit of smoothing-out the disturbances threatening high-resolution analog parts, including sensitive read-margins of logic parts.
Power analysis is best performed in the time domain, while noise resilience is best analyzed over the spectral domain.
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