8-bit 16-bit 32-bit Core

All performances are given in TSMC 18 µm process - other process nodes are available on request

			PERFORMANCES						DOWNLOAD
CORE	Speed /80C51¹	DSP	Area ³ mm²	Processing power ² DMIPS/MHz	Code density ² Bytes	Consumption ³		Leakage Curent ³ µW	Seduction*	Charm*
CORE	Speed /80C51¹	DSP	Area ³ mm²	Processing power ² DMIPS/MHz	Code density ² Bytes	µA/MHz	µA/DMIPS	Leakage Curent ³ µW	Seduction*	Charm*
8-bit
Flip8051-Wind	x3	N	0.06	0.017	12 974	21	1 235	1.5	Presentation Sheet Product Primer	Modelsim SMASH
Flip8051-Cyclone	x9	N	0.12	0.047	12 974	51	1 085	2.4	Presentation Sheet Product Primer	Modelsim SMASH
Flip8051WHIRL (16)-Cyclone	x12.5	Y	0.17	0.047	12 974	57	1 213	4.2	Presentation Sheet Product Primer	Modelsim SMASH
16-bit
Flip80251-Typhoon	-	N	0.25	0.296	6 720	84	284	4.5	Presentation Sheet Product Primer	Modelsim SMASH
32-bit
FlipAPS32 - 051H	-	N	0.18	0.710	7 360	34⁽⁴⁾	48	2.8	Presentation Sheet Product Primer	Modelsim SMASH
Microcontroller Configuration
Flip80515	x1								Product Primer on request
Flip83152	x1								Product Primer on request

All area, power, and frequency numbers are subject to changes based on each user's chosen process technology, cell library, and EDA solutions.
¹ Acceleration based on the overall instruction set of 8051,
² Dhrystone v2.1 / 200 loops,
³ Typical case conditions - 1.8, 25C including wire load and clock tree consumption (+30%) using SESAME uHDvLC library,
⁴ with automatic clock gating

Overview Partnerships

Emulation Core Peripherals Testbench