Benchmark for Microcontroller
Virtual Clock: The Flip8051 Cyclone running at 200 MHz
corresponds to a standard 80C51 running at 1.4 GHz !!
Performance increase compared to the legacy 80C51 running at 12 MHz: x 116 !!
The Dhrystone V1.1 benchmark is an industry standard designed to measure application-programming performance.
This benchmark program was developed by Reinhold P. Weicker (12/01/84), translated from ADA by Rick Richardson, and updated in 1986 (01/06).
The benchmark includes weighted percentages of procedural calls, loops, integer assignments, integer arithmetic and logical operations. It evaluates not only microprocessor performance but also compiler efficiency.
The results indicated are cormputed with a processing loop equal to 200 Dhrystones.
To determine the Dhrystone V1.1 MIPS rating, the Dhrystone V1.1 result is divided by the number 1757 (the Dhrystones result achieved on a VAX 11/780). 1 DMiPS = 1757 DHRYSTONE
By communicating a false ratio of Dhrystone/MIPS, anyone may increase artificially the performance of a microprocessor: It is a pity to discover the truth later on silicon!
Acceleration with the DSP coprocessors
The Dhrystone benchmark does not take into consideration the specific DSP instructions for 16-bit words implemented in the Whirl options (MAC16, MPY16, BSH...) enabling to boost the execution of specific application program.
Program for computing a 2nd order Butterworth filter of the form:
H(z) = (b0 + b1 * z -1 + b2 * z -2) / (1 + a1 * z -1 + a2 * z -2)
The Whirl Coprocessors are the better and the cheaper solutions for:
Boosting the execution of complex mathematical functions
Reducing drascally the size of the Application Program
Speed Optimization
- Higher Speed for your Application Program through division by 2 to 30 of its duration, while maintaining the same SoC frequency:
Execution duration of the Dhrystone application program
Power Consumption Optimization
- Lower the Power Consumption of your SoC through division by2 to 30 of Clock frequency while maintaining the duration of your Application Program
Frequency used to run the Dhrystone application program
with the same duration
CHOICE of BENEFITS: The extra processing power can be used, either to increase the performance of a 80C51/C251-based application, or to run the same application at a lower clock frequency for saving power! |
- Reduce your Power Consumption through program selection of dedicated clocks with the Clock/Power Management Unit: CPMU & ECPMU (exclusive from Dolphin)
Through the CPMU and the ECPMU, the user can select a high-speed clock (e.g. 100 MHz) for the sub-routines of the program requiring High performances, and a low-speed clock (e.g. 10 MHz) for the other parts of the application program in order to reduce the total SoC power consumption.
Reduction on Power consumption!
Rc = Y x (Fn-Fr) / Fn = 70% x (100-10)/100 = 63%
Y = % of time where the application program is running
at the Reduced Frequency versus the Nominal frequency
The ECPMU offers the capability:
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to avoid working at a fixed frequency determined by a compromise between Performance and Consumption,
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to use a programmable frequency divider, enabling the division of clocks by 2 to 16384,
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to switch off the clock by programming, for example when the Flip8051 is in power down mode.
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to further reduce the power during idle mode by reducing the frequency of the System Clock during this mode,
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to exit from the Power Down mode by a dedicated Input instead of a Reset,
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to use an external Ring Oscillator during an initialization phase of the main clock in order to speed-up the wake-up of the µC after a Power Down
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